Optimized FPGA Based Modified MFCC Architecture Using Time Division Multiplexed FFT Processing

Muthumari M; R. S.  Valarmathi

doi:10.35882/jeeemi.v8i4.1938

Muthumari M Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Tamil Nadu, India https://orcid.org/0000-0002-5424-5738
R. S. Valarmathi Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Tamil Nadu, India https://orcid.org/0000-0003-4676-0729

DOI: https://doi.org/10.35882/jeeemi.v8i4.1938

Abstract

Speech recognition technologies are becoming more common in automation, observation of safeguards, and interaction between human and machine. An efficient pre-processing stage is incorporated to enhance the overall performance of the proposed speech recognition framework. This stage focuses on eliminating background noise, improving speech signal quality, and extracting informative acoustic features that effectively characterize the input speech. The resulting robust feature representations significantly improve recognition accuracy while increasing the reliability and efficiency of the subsequent processing stages. Mel Frequency Cepstral Coefficients (MFCCs) are widely used because they are good at capturing speech features that are important to the way we hear things. This paper presents an enhanced MFCC architecture that integrates dual windowing and a Time Division Multiplexed Fast Fourier Transform (TDM-FFT) utilising an Approximate Radix-4 Distributed Arithmetic multiplier, aimed at diminishing hardware complexity while maintaining performance in noisy circumstances. The architecture is made to improve speech quality with less delay and more energy efficiency. The experimental results show that the hardware is being used more efficiently. There is a 50% reduction in LUT/ALM usage, a 60% reduction in DSP resources, and a 50% reduction in power consumption compared to the existing architecture. The results of ASIC synthesis confirm that the proposed architecture is compact which reduces latency by 69% (1024 to 320 cycles) and improves throughput. The proposed architecture reduces the core silicon area by approximately 50%, resulting in improved hardware resource utilization and energy efficiency. These advantages make it highly suitable for real-time embedded speech recognition applications with stringent constraints on silicon area, power consumption, and processing latency.

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References

W. Liu, “Voice control system based on Zynq FPGA,” Journal of Physics: Conference Series, vol. 1631, no. 1, p. 012177, 2020. doi: 10.1088/1742-6596/1631/1/012177

A. S. Haq, M. Nasrun, C. Setianingsih, and M. A. Murti, “Speech recognition implementation using MFCC and DTW algorithm for home automation,” Proceedings of the Electrical Engineering Computer Science and Informatics, vol. 7, no. 2, pp. 78–85, 2020. doi: 10.11591/eecsi.v7.2041

S. Khamlich, F. Khamlich, I. Atouf, and M. Benrabh, “Performance evaluation and implementations of MFCC, SVM and MLP algorithms in the FPGA board,” International Journal of Electrical and Computer Engineering Systems, vol. 12, no. 3, pp. 139–153, 2021. doi: 10.32985/ijeces.12.3.3

S. P. S. Bibin, A. X. Glittas, and L. Gopalakrishnan, “A low latency modular level deeply integrated MFCC feature extraction architecture for speech recognition,” Integration, vol. 76, pp. 69–75, 2021.doi: 10.1016/j.vlsi.2020.09.002

N. A. Al Hindawi, I. Shahin, and A. B. Nassif, “The exploitation of multiple feature extraction techniques for speaker identification in emotional states under disguised voices,” in Proc. 14th Int. Conf. Developments in eSystems Engineering (DeSE), 2021, pp. 269–273. doi: 10.1109/DeSE54285.2021.9719357

M. K. Gourisaria, R. Agrawal, M. Sahni, and P. K. Singh, “Comparative analysis of audio classification with MFCC and STFT features using machine learning techniques,” Discover Internet of Things, vol. 4, no. 1, p. 1, 2024. doi: 10.1007/s43926-023-00049-y

H. Zhang, H. Li, W. Chen, and H. Han, “Feature extraction of speech signal based on MFCC,” Journal of Physics: Conference Series, vol. 2584, no. 1, p. 012143, 2023. doi: 10.1088/1742-6596/2584/1/012143

Li Qin, Yuze Yang, Tianxiang Lan, Huifeng Zhu, Qi Wei, Fei Qiao, Xinjun Liu, and Huazhong Yang., “MSP MFCC: Energy efficient MFCC feature extraction method with mixed signal processing architecture for wearable speech recognition applications,” IEEE Access, vol. 8, pp. 48720–48730, 2020.doi: 10.1109/ACCESS.2020.2979799

Deshmukh, Aditya, Arman Khan, Vedika Patil, and Kishor Bhangale. "Real Time FPGA Implementation for Speech Feature Extraction." In 2025 6th International Conference for Emerging Technology (INCET), pp. 1-7. IEEE, 2025. doi: 10.1109/INCET64471.2025.11140105

Abdusalomov, Akmalbek Bobomirzaevich, Furkat Safarov, Mekhriddin Rakhimov, Boburkhon Turaev, and Taeg Keun Whangbo., “Improved feature parameter extraction from speech signals using machine learning algorithm,” Sensors, vol. 22, no. 21, p. 8122, 2022. doi: 10.3390/s22218122

J. Vreča, R. Pilipović, and A. Biasizzo, “Hardware–software co-design of an audio feature extraction pipeline for machine learning applications,” Electronics, vol. 13, no. 5, p. 875, 2024. doi: 10.3390/electronics13050875

X. Mu and C. H. Min, “MFCC as features for speaker classification using machine learning,” in Proc. IEEE World AI IoT Congress (AIIoT), 2023, pp. 566–570. doi : 10.1109/AIIoT58121.2023.10174566

Hamouda, Salim, Samir Hamdani, Hamid Khelfi, Kamel Boudjit, Drid Mohamed Dhia Eddine, and Kassa Baghdouche., “Real time FPGA implementation of FFT architecture utilizing a single butterfly calculator: Application on rotor bars fault detection in induction motor,” in Proc. 12th Int. Conf. Systems and Control (ICSC), 2024, pp. 418–423. Doi: 10.1109/ICSC63929.2024.10928791

S. Bae, H. Kim, S. Lee, and Y. Jung, “FPGA implementation of keyword spotting system using depthwise separable binarized and ternarized neural networks,” Sensors, vol. 23, no. 12, p. 5701, 2023.doi: 10.3390/s23125701

Shan, Weiwei, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, and Jun Yang., “A 510 nW wake up keyword spotting chip using serial FFT based MFCC and binarized depthwise separable CNN in 28-nm CMOS,” IEEE Journal of Solid State Circuits, vol. 56, no. 1, pp. 151–164, 2020.doi: 10.1109/JSSC.2020.3029097

Wassi, Guy, Sylvain Iloga, Olivier Romain, and Bertrand Granado. "FPGA based real time MFCC extraction for automatic audio indexing on FM broadcast data." In 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 1-6. IEEE, 2015. doi: 10.1109/DASIP.2015.7367253

Dao, V.-L., Nguyen, V.-D., Nguyen, H.-D., Hoang, V.-P. (2017). “Hardware Implementation of MFCC Feature Extraction for Speech Recognition on FPGA”. In: Nguyen, N.T., et al. (eds) Advances in Information and Communication Technology. AISC, vol. 538, pp. 248–254. Springer, Cham. doi:10.1007/978-3-319-49073-1_27

Barma Venkata RamaLakshmi and Fazal Noorbasha. “FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm” [J]. Int J Performability Eng, 2021, 17(6): 552-558.doi: 10.23940/ijpe.21.06.p8.552558

Nagesh, Patnala Uma Mehar Sai, and Vella Satyanarayana. "Design of Radix-4 Booth (Radix 256 booth encoding) Multiplication Algorithm." In 2026 4th International Conference on Knowledge Engineering and Communication Systems (ICKECS), pp. 1-6. IEEE, 2026. doi: 10.1109/ICKECS70176.2026.11528088

Srinivas, Nettimi Satya Sai, Nagarajan Sugan, Lakshmi Sutha Kumar, Malaya Kumar Nath, and Aniruddha Kanhe. "FPGA Based Design of a Ready to Use and Configurable Soft IP Core for Frame Blocking Time Sampled Digital Speech Signals." Electronics 13, no. 21 (2024): 4180.doi: 10.3390/electronics13214180

Yang, Yucheng, Shukai Duan, and Lidan Wang. "An FPGA Accelerated Approach to Direct Waveform Processing for Low Power Keyword Spotting." In Proceedings of the International Conference on Image Processing, Machine Learning and Pattern Recognition, pp. 157-161. 2024.doi: 10.1145/3700906.3700931

Shihab, Md Shazzad Hossain, Shuvra Aditya, Jahangir Hossain Setu, K. M. Imtiaz Ud Din, and Md Iftekharul Alam Efat. "A hybrid GRU CNN feature extraction technique for speaker identification." In 2020 23rd International conference on computer and information technology (ICCIT), pp. 1-6. IEEE, 2020.doi: 10.1109/ICCIT51783.2020.9392734

Sun, Chang, Zhiqiang Que, Vladimir Loncar, Wayne Luk, and Maria Spiropulu. "da4ml: Distributed arithmetic for real-time neural networks on fpgas." ACM Transactions on Reconfigurable Technology and Systems 19, no. 1 (2026): 1-27. doi: 10.1145/3777387

Heriyanto, H., and D. A. Irawati. "Comparison of Mel Frequency Cepstral Coefficient (MFCC) Feature Extraction, With and Without Framing Feature Selection, to Test the Shahada Recitation." In RSF Conference Series: Engineering and Technology, vol. 1, no. 1, pp. 335-354. 2021.doi: 10.31098/cset.v1i1.395.

Mohanty, Basant Kumar. "Efficient approximate multiplier design based on hybrid higher radix booth encoding." IEEE journal on emerging and selected topics in circuits and systems 13, no. 1 (2022):165-174.doi: 10.1109/JETCAS.2022.3229831

Aggarwal, Apeksha, Akshat Srivastava, Ajay Agarwal, Nidhi Chahal, Dilbag Singh, Abeer Ali Alnuaim, Aseel Alhadlaq, and Heung No Lee. "Two way feature extraction for speech emotion recognition using deep learning." Sensors 22, no. 6 (2022): 2378.doi: 10.3390/s22062378

Tripathi, Astha, and Poonam Rani. "Multilingual speech emotion recognition using IGRFXG–Ensemble feature selection approach." Applied Acoustics 240 (2025): 110905. doi: 10.1016/j.apacoust.2025.110905

Lu, Lu, Chi Liu, Duo Li, Xuexian Liu, Yubo Li, Lei Cheng, and Xu Zheng. "Fusion of Log Mel spectrogram and acoustic features for driver speech emotion recognition." Expert Systems with Applications (2025): p 131021 vol. 307. doi: 10.1016/j.eswa.2025.131021

Mokhtar, A. S., C. S. Ping, MF Md Din, N. Makmor, and M. Mahadi. "Implementation of Booth multiplier algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan 1 (2021): pp 161-165. doi: 10.17576/jkukm-2021-si4(1)-20

Yu, Baoying, Mengjie Luo, Dingyi Wang, Xiaoqin Wang, and Shushan Qiao. "A low power and low latency speech feature extractor based on time domain filter bank." IEEE Transactions on Circuits and Systems II: Express Briefs 71, no. 3 (2023): pp 1421-1425.doi: 10.1109/TCSII.2023.3324337

Muthumari, M., and R. S. Valarmathi. "Optimal Realization of Parallel MAC Based Adaptive FIR Filter Using a Gaussian Mutation on Quantum Behaved Particle Swarm Optimization Algorithm." Journal of Circuits, Systems and Computers 34, no. 15 (2025): 2550330.doi: 10.1142/S021812662550330X

Choudhary, Tripti, Vishal Goyal, and Atul Bansal. "Enhanced lstm network with semi supervised learning and data augmentation for low resource ASR." International Journal on Smart Sensing and Intelligent Systems Vol. 18, Iss. 1, (2025). doi:10.2478/ijssis-2025-0009

D. Kale, G. Ganjre and R. Udani, "A Proposed Real Time FPGA System Using MFCC Features for Acoustic Anti Poaching Monitoring," 2026 International Conference on Communication, Computing and Emerging Technologies (IC3ET), Vasai, India, 2026, pp. 215-220, doi: 10.1109/IC3ET64989.2026.11467226.

Bonet Solà, Daniel, and Rosa Ma Alsina Pagès. 2021. "A Comparative Survey of Feature Extraction and Machine Learning Methods in Diverse Acoustic Environments" Sensors 21, no. 4: 1274. https://doi.org/10.3390/s21041274

Li et al., "MSP MFCC: Energy Efficient MFCC Feature Extraction Method With Mixed Signal Processing Architecture for Wearable Speech Recognition Applications," in IEEE Access, vol. 8, pp. 48720-48730, 2020, doi: 10.1109/ACCESS.2020.2979799

Kia, Ali, Ajan Ahmed, and Masudul H. Imtiaz. 2026. "FPGA Based Implementations of Biometric Recognition: A Review" Electronics 15, no. 10: 2145. https://doi.org/10.3390/electronics15102145

Tsai, TH., Wang, CL. “GMM Based Speaker Verification System with Hardware MFCC in SoC Design”.Multimed Tools Appl 83, 56991–57010 (2024).https://doi.org/10.1007/s11042-023-17561-6.

M. Kotari, Sharath, S. Kanabargi, S. Alori and Y. B, "A Review on AI Acceleration with FPGA and ASICs: A Comparative Study," 2025 IEEE 4th International Conference on Data, Decision and Systems (ICDDS), Dharwad, India, 2025, pp. 212-215, doi: 10.1109/ICDDS67737.2025.11344680.

Konstantopoulou, Evangelia, George Athanasiou, and Nicolas Sklavos. "Review and analysis of FPGA and ASIC implementations of NIST lightweight cryptography finalists." ACM Computing Surveys 57, no. 10 (2025): 1-35. https://doi.org/10.1145/3721122.

Lou, Haozhe. "Comparative analysis and enhancement of FPGA and ASIC performance in targeted applications." In International Conference on Artificial Intelligence and Communication Technology, pp. 295-308. Singapore: Springer Nature Singapore, 2024. doi:10.1007/978-981-96-0096-0_23.